From a Vectrex point of view: (internal.txt)
6522A
This device is used to control all of the vectrex peripheral devices, such as the Keypads, Vector generator, DAC, Sound chip, etc.
The A port is used as a BUS and goes directly to the DAC input and sound chip input pins D0-D7. The DAC will output whatever value is on this port.
The B Port is used in the following way:
PB0 - SWITCH Switch Control, enables/disables the analog multiplexer,
see Vector drawing hardware description
PB1 - SEL0 Controls multiplexer channel select, see section on
PB2 - SEL1 Vector drawing.
PB3 - BC1 Chip Select Signal for the AY-3-8192 Sound Chip
PB4 - BDIR Read/Write Signal for the AY-3-8192 Sound Chip
PB5 - COMPARE Feedback from the OP-AMP that does the comparison
for calculation of analog joystick positions.
PB6 - ??? This line is fed to the cartridge connector. It is
likely that this line was to have been used as a ROM
bank select for cartridges greater than 32K.
PB7 - ~RAMP This line controls part of the vector drawing
hardware, see later. It is an active LOW signal.
The 6522PIA Has a number of control lines that are sometimes used as handshake lines as the can generate interrupts, but on the vectrex they are used to control the vector drawing hardware
CA1 - IO7 This line is connected to the IO7 line of the AY-3-8192
sound chip. My guess it is used to generate an
interrupt to the CPU. See the AY-3-8192 description
for more details on IO7.
CA2 - ~ZERO Connected to the integrators that form part of the
vector drawing hardware. This line will cause them
to be zero'd (both X and Y) and has the effect of
bringing the beam back to the centre of the CRT. It
is an active LOW signal. See Vector hardware section
for more info.
CB1 - Not Connected
CB2 - ~BLANK This Active LOW signal is the BEAM ON/OFF signal
to the Vector drawing hardware, and is used to hide
the beam when it is being positioned for re-draw.
See Vector hardware section for more info.
Some Vectrex defines: VIA_port_b EQU $D000 ;VIA port B data I/O register * 0 sample/hold (0=enable mux 1=disable mux) * 1 mux sel 0 * 2 mux sel 1 * 3 sound BC1 * 4 sound BDIR * 5 comparator input * 6 external device (slot pin 35) initialized to input * 7 /RAMP VIA_port_a EQU $D001 ;VIA port A data I/O register (handshaking) VIA_DDR_b EQU $D002 ;VIA port B data direction register (0=input 1=output) VIA_DDR_a EQU $D003 ;VIA port A data direction register (0=input 1=output) VIA_t1_cnt_lo EQU $D004 ;VIA timer 1 count register lo (scale factor) VIA_t1_cnt_hi EQU $D005 ;VIA timer 1 count register hi VIA_t1_lch_lo EQU $D006 ;VIA timer 1 latch register lo VIA_t1_lch_hi EQU $D007 ;VIA timer 1 latch register hi VIA_t2_lo EQU $D008 ;VIA timer 2 count/latch register lo (refresh) VIA_t2_hi EQU $D009 ;VIA timer 2 count/latch register hi VIA_shift_reg EQU $D00A ;VIA shift register VIA_aux_cntl EQU $D00B ;VIA auxiliary control register * 0 PA latch enable * 1 PB latch enable * 2 \ 110=output to CB2 under control of phase 2 clock * 3 > shift register control (110 is the only mode used by the Vectrex ROM) * 4 / * 5 0=t2 one shot 1=t2 free running * 6 0=t1 one shot 1=t1 free running * 7 0=t1 disable PB7 output 1=t1 enable PB7 output VIA_cntl EQU $D00C ;VIA control register * 0 CA1 control CA1 -> SW7 0=IRQ on low 1=IRQ on high * 1 \ * 2 > CA2 control CA2 -> /ZERO 110=low 111=high * 3 / * 4 CB1 control CB1 -> NC 0=IRQ on low 1=IRQ on high * 5 \ * 6 > CB2 control CB2 -> /BLANK 110=low 111=high * 7 / VIA_int_flags EQU $D00D ;VIA interrupt flags register * bit cleared by * 0 CA2 interrupt flag reading or writing port A I/O * 1 CA1 interrupt flag reading or writing port A I/O * 2 shift register interrupt flag reading or writing shift register * 3 CB2 interrupt flag reading or writing port B I/O * 4 CB1 interrupt flag reading or writing port A I/O * 5 timer 2 interrupt flag read t2 low or write t2 high * 6 timer 1 interrupt flag read t1 count low or write t1 high * 7 IRQ status flag write logic 0 to IER or IFR bit VIA_int_enable EQU $D00E ;VIA interrupt enable register * 0 CA2 interrupt enable * 1 CA1 interrupt enable * 2 shift register interrupt enable * 3 CB2 interrupt enable * 4 CB1 interrupt enable * 5 timer 2 interrupt enable * 6 timer 1 interrupt enable * 7 IER set/clear control VIA_port_a_nohs EQU $D00F ;VIA port A data I/O register (no handshaking)